Synopsys

Qualification :

• BE/ B.Tech/ ME/ M.Tech (IT/ CSE/ ECE/ EEE) from 2011/ 2012 batches with aggregate of 70% and above.

Job Description :

• Architecture exploration of the sub-blocks within one of these IPs to optimize for area, speed and power.
• VLSI Design & verification of these sub-blocks/exploration of latest features and standards
• Selected candidates will work with the Design Compiler R&D team to implement synthesis product capabilities including but not limited to Synthesis for Multi-Voltage design, usability and infrastructure enhancements.
• Will have to support existing functionality and strive to improve the quality and maintainability of the software. Development will be in C.
• Candidates will require performing first level debugging on any issues hit during development, using standard tools available in-house. As part of the job, the engineer will also design and develop test cases in VHDL/Verilog to test the features/bugs fixed by the individual.

• Will also be responsible to validate the code changes across the existing Regression testing system and QoR suite.

Skills Required :

• Candidates should have excellent C programming skills, thorough in Data Structures and Algorithms and good Digital Design knowledge.
• Knowledge of PERL, Tcl and Shell scripting; debugger (gdb); HDLs like VHDL/Verilog are an added advantage.
• Should be a self-learner, committed, good team player with good written/oral communication skills