Eligibility:
B.E/ B. Tech (ECE, EEE, CSE, IT) - Upto 2022 Passouts
Roles and Responsibilities:
- To play the role of Verification engineer at the Block level, Chip level Functional verification.
- Develop verification test plans from design specifications.
- Development of test environments using System Verilog and UVM verification methodologies.
- Create multiple test cases as per the test plan and launch regressions.
- Generate Code/Functional coverage, analyze coverage results and correlate with the test plan.
- Working with the design team members to identify and quickly resolve problems with the design.
- Communicate regularly with the team members to resolve issues and report status.
- Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges.
Work Location: Siruseri, Chennai.
Salary(CTC): CTC: 4LPA to 6LPA.
Probation (3Months): Food and Accommodation are Free for 3 months during the training period.
Interview Process:
1. Assessment
2. Technical GD
3. Technical One on One
4. HR