Digital Design Engineer Jobs in Bangalore - Texas Instruments
Job Description
STA Lead:6/7+ years
6+years of relevant experience
- Strong SOC timing signoff closure profile with hands-on experience on 4+ tape outs.
- Strong knowledge on constraints development and validation.
- Strong understanding of margins/derates.
- Should be able to create both clock and data timing ECOs. Manual and tool based flows.
- Experience on Cadence tools (Tempus/TSO) will be added advantage.
- Must have strong synthesis knowledge.
- Multimode multi corner signoff closure experience is must.
- Must have SOC level IR drop closure experience on 3+ devices
- Strong SOC level physical verification expertise with minimum of 3+ tapeouts
- Strong knowledge on PnR flows.
- Experience on Cadence tools (Voltus) will be added advantage
Job Particulars
Role engineer core non it
Who can apply Experienced (3+ Years)
Hiring Process Face to Face Interview
Employment Type0
Job Id1073428
Job Category Core Technical
Locality Address
State Karnataka
Country India
About Company
Texas Instruments
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