v Good overall Software development skills with sound knowledge of C/C++ and data structures / algorithms needed
v The work will involve problem analysis/understanding, working out solutions/strategy, implementation & testing.
v Knowledge of HDL (hardware descriptive languages like Verilog/VHDL/System Verilog) needed, preferably both from synthesis and simulation perspective
v Expertise in modern testbench/verification methodologies especially SystemVerilog UVM, SystemC based methodologies is a plus.
v B.Tech/ M.Tech in EE/ECE or in the related field with reputed colleges like IITs/NITs/DCE/BITS/IIITs with 7+ years of experience