Design Verification Engineer Job in Niksperri Technologies at Whitefield, Bangalore

Design Verification Engineer

Niksperri Technologies

0 Years

Not disclosed

Expired

Posted: 04 Oct 22

Job Description

We have an urgent requirement for Design Verification Engineer

Job role - Design Verification Engineers

Job Location - Bangalore

Academic Criteria - M.E/ M.Tech with 70%

Year of passing M.E/M.Tech - 2020/2021/2022

Technical Skills -

Digital, Verilog, System Verilog & UVM.Protocols- AXI, AMBA & I2CComplex Protocols - PCIe, Ethernet, USB (Knowledge in these are an added advantage)

More information about this Design Verification Engineer Job

Please go through the below FAQs to get all answers related to the given Design Verification Engineer job

What are the job requirements to apply for this Design Verification Engineer job position?
- Ans: A candidate must have a minimum of fresher as an Design Verification Engineer

What is the qualification for this job?
- Ans: The candidate can be a Graduate from any of the following: ME/M.Tech
What is the hiring Process of this job?
- Ans: The hiring process all depends on the company. Normally for an entry level, hiring the candidate has to go for Aptitude, GD (If they look for communication),Technical test and face to face interviews.
This Design Verification Engineer is a work from home job?
- Ans: No ,its not a Work from Home Job.
How many job vacancies are opening for the Design Verification Engineer position?
- Ans: There are immediate 1 job openings for Design Verification Engineer in our Organisation.

Job Particulars

Role engineer core non it

Education ME/M.Tech(Electrical Engineering, Electronics & Communication Engineering, Embedded System Technologies, VLSI Design)

Who can apply Freshers

Hiring Process Face to Face Interview

Employment TypeFull Time

Job Id1591219

Job Category Core Technical

Locality Address Whitefield

State Karnataka

Country India

About Company

NikSperri Offers Semiconductor Services in form of R & D and provides Staff Augmentation and ODC model to Chip Product Companies. Already in delivering stages of IPs in Analog Layout Domain. We are Moving towards IP developments in Verification Domain in cutting edge technologies.

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