Engineer Computing Optimization Jobs in Chennai - KLA

Responsibilities

Position: Ph.D./MS NCG position: FPGA HLS C/C++ Device Level programming

KLA is hiring engineers for its Advanced Computing Labs in Chennai, India. KLA ACL is at our new research center in the IITM, Research Park. The goal of the center is to conduct computational research in parallel and distributed sub-systems and deploy them to KLA’s advanced semi-conductor platforms that are used for inspection and metrology tasks in leading fabs. These efforts are part of a larger global initiative at KLA to scale up its AI + HPC + cloud infrastructure.

What will you be responsible for?

As part of this elite R&D team, the job entails understanding core algorithms that have to expressed in various parallel computing constructs particularly HPC accelerators such as FPGAs. The first step in optimizing will be to theoretically model break-down of our AI algorithms and model it in terms of available bandwidth, computational FLOPS etc.

Historically FPGAs have been programmed in HW RTL languages such VHDL and Verilog. In these projects, one of the main areas of research are to see if newer HLS (Higher Level Synthesis) tools sets such as Xilinx’s Vivaldo/Vitis that allow computation to be expressed in the C/C++ language can be competitive with RTL. The project requires engineers with a very strong background in traditional FPGA programming to map those computations into the HLS C++ language and explore to see how much performance is achieved relative to RTL while enabling significant programmer productivity.

While the initial focus of the team will be on lower level module productivity using Vivaldo/Vitis toolsets, it is also the intent to see if one can use higher level programming models such as SYCL/DPC++/TriSycl to achieve similar performance.

Qualifications

What we would like to see in you?

• New/recent College graduates in Ph.D. (preferred), Dual Degree MS in EE, CS or CSE. Bachelors graduates will also be considered.
• A person who has a strong background in computer architecture, and in particular with a focus on high performance parallel processing at the device level FPGAs.
• FPGA related technical skills including FPGA chip design, Verilog/VHDL for FPGA, FPGA tools design and HLS.
• A strong background in C/C++ programming with a good understanding of the C++ computational models.
• The candidate should have a very strong mental model of computational loads and mapping different algorithms to parallel architectures.
• Bonus skills will be exposure / experience in GPU programming.
• Reasonable comfort level with the Linux operating system at the user level.
• Exposure to multiprocessor and multithreading concepts
• Some familiarity with GPU programming such as CUDA, OpenCL or SYCL.
  

The position also requires a person with significant communication, initiative and the ability to navigate from relatively high-level requirements to low level computational models.

Bonus Skills

Any prior experience in KLA domains such as wafer inspection coupled with programming in CUDA or AVX will be a very plus. Additionally, any experience in optimizing large scale signal or computer vision algorithms would also be a major plus. It

Experience in large scale distributed HPC systems, proven experience in Docker and Container orchestration and any expertise in AI Frameworks (TensorFlow) will also be welcome.

Finally a strong background in Modern C++ concepts (C++ 11 through C++ 17), STL library would also be a way to stand out from the crowd.