Strong knowledge of DFT architectures & methodologies which includes Scan, ATPG, Mbist, BScan, IO DFx, analog DFT, JTAG, Boundary scan etc and proven knowledge of Verilog & System Verilog, RTL design and micro-architecture skills. Strong knowledge of SoC tools/methodology ( VCS*, Synthesis, Spyglass, Tessent Industry standard ATPG/MBIST tools design compiler etc. and also DFT design on Physical design highly desirable). In addition, this position requires interaction and fulfilling the requirements of Intel's post-silicon/ATE teams, Silicon Debug and understanding HVM (High Volume Manufacturing) requirements. Strong debug skills and demonstrated experiences in Perl & TCL scripting are a must. Strong Communications skills and the ability to effectively work with cross functional teams across geographies are required. We are looking for smart and enthusiastic Engineers to develop Design For Testability for our SOCs.
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The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
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