Verification & Design Engineer Jobs in Bangalore - Atria Logic

Verification Design Engineer

Atria Logic

Not disclosed

Expired

Posted: 29 Aug 18

Job Description

Strong knowledge on Digital design concepts with RTL implementation (Verilog/VHDL)· FPGA/ASIC tool flows for Logic Synthesis, STA and Frontend Design.· Expertise in RTL top level integration and should have excellent debugging skills.· As a Verification engineer able to work on full chip Verification and OVM/UVM Methodology,· System Verilog, passing test cases, test benches, Building environment is must· Good knowledge of Functional coverage using HVL language features or assertions a plus.· Good in concepts of code coverage and Functional coverage.· Strong domain knowledge on PCI/PCIe Verification /Ethernet MAC/DDR/PHY· Knowledge to develop required script to complete verification using Perl, Shell or Python â€“ preferable.